The invention relates to a method and a circuit arrangement for testing data processors. The invention is particularly useful with telephone switching systems having peripheral units connected to a control center over a bus line system.
Program controlled systems having electronic central control units have increasingly been employed in telecommunication switching. Conventional designs of such central control units consist of a plurality of individual units structured into a hierarchy and involve central and peripheral units. It is common practice to connect such peripheral units to the central unit over a bus line system. The peripheral units are all connected in the same manner to such a bus line system. Digital addresses are communicated from the central unit to the address inputs of all the peripheral units over the bus line system to select and activate one of a plurality of peripheral units. The information content of a specified transmitted address code can be screened by means of an address decoder allocated to each individual peripheral unit so that only one of a plurality of peripheral units is activated.
For reasons of operational reliability and in an effort to minimize down time, it is common practice to routinely test all the essential parts of an electronic central control unit. Checks of the bus line systems and of the individual address decoders in the peripheral units are particularly significant, because an error in this area can render the entire central control unit inoperative.
To test a data processor having a central processor and a plurality of storage units which are addressable over a common bus line, present techniques (cf. West German Auslegeschrift 2,048,670) determine if an addressed or a non-addressed storage unit transfers an incorrect answer to a storage read instruction supplied by the processor over the common bus line. To achieve this, a read instruction is transmitted from the central processor over the common bus line so as to obtain a predetermined bit pattern stored in a prespecified storage location of the addressed storage unit. This read instruction is assigned individually to the addressed storage unit. In the processor, a bit pattern specially assigned to the addressed storage unit is compared with the bit pattern obtained through said processor over the bus line in order to deduce an error pattern. With this process, it can be determined if a bit pattern obtained over the bus line contains bits pertaining to identifier bit patterns specially assigned to other storage units. This prior art method thus enables the detection of address errors.
It is an object of this invention to provide a method and circuit arrangement by which double addressings in the periphery of the bus line system can be detected.
Another object is to provide means and method for determining if incorrect answerbacks from the periphery in reaction to test instructions are caused by an incorrectly activated unit or by malfunctions in the addressed unit or in the bus line system.
A further object is to provide a testing method which can be performed fully automatically without deleteriously affecting the normal operation of the central control unit.
Still another object is to provide a method and circuit arrangement in which the allocation of address codes is not subject to any restriction, thus resulting in optimum utilization of the address circuit of the bus line system and flexibility in the design of data processors.